1. Field of the Invention
This invention relates to a cell library for a semiconductor integrated circuit design, more particularly cell library for a gate array or a standard cell arrangement including BiCMOS cells.
2. Description of the Prior Art
There are three types of conventional design methods for LSIs.
The first is the method wherein all processes, from positioning the elements to the wiring for a transistor or the like, are performed anew each time on a semiconductor substrate. This is known as the full custom method and exhibits the features of high performance and good efficiency in forming a small chip. On the other hand, this method has the drawback that development requires a long time and much labor.
The second method is the opposite of the first, in as much as the elements of the transistor or the like are provided in advance in the form of an array on the substrate of the semiconductor, already prepared as a wafer, and only the wiring between the elements must be decided, according to the application. This is referred to as the gate array method. The wiring for forming the necessary blocks (cells) to provide the various functions using this array is designed in advance and prepared in the form of a library. The designer combines the appropriate cells with reference to the library, and designs the intercell wiring. Following this, the actual wiring required with this method is extremely easy.
Intermediate to these two methods is the third method, known as the standard cell method. In this case, the arrangement of the elements and the wiring within one cell are designed as the optimum for each cell, and the designer, as a result, requires a shorter development period than for the full custom approach because only the combining of the cells and their interwiring need be performed. However, the arrangement of The cells on the semiconductor substrate from the stage of preparing the wafer is required, and more time is required to complete the LSI than for the gate array.
A conventional CMOS gate array or CMOS standard cell is illustrated in FIG. 1. A basic cell 101 is arranged to form a plurality of rows between which a wiring field 103 is interposed. A power source wiring 105 and a power source wiring 107 are formed on the upper and lower ends respectively of the individual cells, and the power wiring is connected automatically between the subjoining cells so that two series of power wiring 105 and 107 are formed, running through the respective rows.
In the development of conventional gate array or standard cells as described above, the utilization of the design method is limited to the circuitry around which the CMOS is centered. If a decision is made to use a circuit including a bipolar element (BiCMOS) as a gate array or standard cell, respectively, in the case where a bipolar element is incorporated in the cell, one cell becomes rather large in size. To add this cell with a bipolar element to a conventional library, certain steps are required. In the most common means considered, the design is modified to adapt each cell of a CMOS library to the BiCMOS size.
However, in this case the entire cell library must be rebuilt, which necessitates a great deal of time and trouble. Furthermore, separate administration of a library for CMOS use and a library for BiCMOS use becomes necessary, which is very inefficient.